Single latch data circuit in a multiple level cell non-volatile memory device

ABSTRACT

A single latch circuit is coupled to each bit line in a multiple level cell memory device to handle reading multiple data bits. The circuit is comprised of a latch having an inverted node and a non-inverted node. A first control transistor selectively couples the non-inverted node to a latch output. A second control transistor selectively couples the inverted node to the latch output. A reset transistor is coupled between the inverted node and circuit ground to selectively ground the circuit when the transistor is turned on.

RELATED APPLICATIONS

This application is a Continuation of U.S. application Ser. No.11/506,428 (allowed), filed on Aug. 18, 2006, the contents of which areincorporated by reference herein in their entirety, which claims thebenefit of the priority date of Italian Patent Application Serial No.RM2006A000074, entitled “SINGLE LATCH DATA CIRCUIT IN A MULTIPLE LEVELCELL NON-VOLATILE MEMORY DEVICE”, filed Feb. 15, 2006.

TECHNICAL FIELD

The present invention relates generally to memory devices and inparticular the present invention relates to non-volatile memory devices.

BACKGROUND

Memory devices are typically provided as internal, semiconductor,integrated circuits in computers or other electronic devices. There aremany different types of memory including random-access memory (RAM),read only memory (ROM), dynamic random access memory (DRAM), synchronousdynamic random access memory (SDRAM), and flash memory.

Flash memory devices have developed into a popular source ofnon-volatile memory for a wide range of electronic applications. Flashmemory devices typically use a one-transistor memory cell that allowsfor high memory densities, high reliability, and low power consumption.Common uses for flash memory include personal computers, personaldigital assistants (PDAs), digital cameras, and cellular telephones.Program code and system data such as a basic input/output system (BIOS)are typically stored in flash memory devices for use in personalcomputer systems.

As the performance and complexity of electronic systems increase, therequirement for additional memory in a system also increases. However,in order to continue to reduce the costs of the system, the parts countmust be kept to a minimum. This can be accomplished by increasing thememory density of an integrated circuit.

Memory density can be increased by using multiple level cells (MLC). MLCmemory can increase the amount of data stored in an integrated circuitwithout adding additional cells and/or increasing the size of the die.The MLC method stores two or more data bits in each memory cell.

A multilevel cell has multiple V_(t) windows that each indicate adifferent state as shown in FIG. 1. Multilevel cells take advantage ofthe analog nature of a traditional flash cell by assigning a bit patternto a specific voltage range stored on the cell. This technology permitsthe storage of two or more bits per cell, depending on the quantity ofvoltage ranges assigned to the cell.

For example, a cell may be assigned four different voltage ranges of 200mV for each range. Typically, a dead space or margin of 0.2V to 0.4V isbetween each range. If the threshold voltage of the cell is within thefirst range, the cell is storing a 11. If the threshold voltage iswithin the second range, the cell is storing a 10. This continues for asmany ranges that are used for the cell. MLC requires tight control ofthe threshold voltages in order to use multiple threshold levels percell.

One critical parameter of MLC flash memory integrated circuits is thetransistor count of the sense amplifier that is used to read theprogrammed values in the cells. The high parallelism of flash memorydevices requires that the same sense amplifier data latch be used atleast one for each bit line being read out of the array. This problem isworse for MLC devices since the circuits need to handle two bits fromeach bit line. This greatly increases the number of transistors requiredfor read-modify-write operations.

Due to intense competition and consumer desire for longer battery lifein electronic devices, manufacturers must constantly find ways to reducethe quantity of components in devices while maintaining reliability. Forthe reasons stated above, and for other reasons stated below that willbecome apparent to those skilled in the art upon reading andunderstanding the present specification, there is a need in the art forreducing the quantity of transistors required in sense amplifier datalatches in MLC memory devices.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a diagram of the threshold voltage distributions of amultiple level cell memory.

FIG. 2 shows a simplified diagram of one embodiment of a NAND flashmemory array.

FIG. 3 shows a schematic diagram of one embodiment of a data latch ofthe present invention.

FIG. 4 shows a diagram of the threshold voltage distribution inaccordance with a page one read operation of the present invention.

FIG. 5 shows a diagram of the threshold voltage distribution inaccordance with a page zero read operation of the present invention.

FIG. 6 shows a schematic diagram of one embodiment of two data latchesin accordance with the programming operation of the present invention.

FIG. 7 shows a schematic diagram of the data latches and supportcircuitry of the present invention.

FIG. 8 shows a block diagram of one embodiment of a memory system of thepresent invention.

FIG. 9 shows a block diagram of one embodiment of a memory module of thepresent invention.

DETAILED DESCRIPTION

In the following detailed description of the invention, reference ismade to the accompanying drawings that form a part hereof and in whichis shown, by way of illustration, specific embodiments in which theinvention may be practiced. In the drawings, like numerals describesubstantially similar components throughout the several views. Theseembodiments are described in sufficient detail to enable those skilledin the art to practice the invention. Other embodiments may be utilizedand structural, logical, and electrical changes may be made withoutdeparting from the scope of the present invention. The followingdetailed description is, therefore, not to be taken in a limiting sense,and the scope of the present invention is defined only by the appendedclaims and equivalents thereof.

FIG. 2 illustrates a simplified diagram of one embodiment for asemiconductor NAND flash memory array of the present invention. Thismemory array is for purposes of illustration only as the presentinvention is not limited any one non-volatile memory technology orarchitecture.

The memory array of FIG. 2, for purposes of clarity, does not show allof the elements typically required in a memory array. For example, onlytwo bit lines are shown (BL1 and BL2) when the number of bit linesrequired actually depends upon the memory density and chip architecture.The bit lines are subsequently referred to as (BL1-BLN). The bit lines(BL1-BLN) are eventually coupled to sense amplifiers (not shown) thatdetect the state of each cell.

The array is comprised of an array of floating gate cells 201 arrangedin series strings 204, 205. Each of the floating gate cells 201 arecoupled drain to source in each series chain 204, 205. A word line(WL0-WL31) that spans across multiple series strings 204, 205 is coupledto the control gates of every floating gate cell in a row in order tocontrol their operation. In one embodiment, an array is comprised of 32word lines. However, the present invention is not limited to any oneword line quantity.

In operation, the word lines (WL0-WL31) select the individual floatinggate memory cells in the series chain 204, 205 to be written to or readfrom and operate the remaining floating gate memory cells in each seriesstring 204, 205 in a pass through mode. Each series string 204, 205 offloating gate memory cells is coupled to a source line 206 by a sourceselect gate 216, 217 and to an individual bit line (BL1-BLN) by a drainselect gate 212, 213. The source select gates 216, 217 are controlled bya source select gate control line SG(S) 218 coupled to their controlgates. The drain select gates 212, 213 are controlled by a drain selectgate control line SG(D) 214.

In the embodiment of FIG. 2, WL0 is at the bottom of the page and WL31is at the top of the page. However, these labels are for purposes ofillustration only as WL0 can also begin at the top of the page with theword line numbers increasing towards the bottom of the page.

Each cell can be programmed as a single bit per cell (i.e., single levelcell—SLC) or multiple bits per cell (i.e., multiple level cell—MLC).Each cell's threshold voltage (V_(t)) determines the data that is storedin the cell. For example, in a single bit per cell, a V_(t) of 0.5Vmight indicate a programmed cell (i.e., logical 0 state) while a V_(t)of −0.5V might indicate an erased cell (i.e., logical 1 state). Multiplelevel cell operation has been discussed previously.

The embodiments of the present invention are not limited to two bits percell. Some embodiments may store more than two bits per cell, dependingon the quantity of different voltage ranges that can be differentiatedon the cell.

During a typical prior art programming operation, the selected word linefor the flash memory cell to be programmed is biased with a series ofprogramming pulses that start at a voltage (e.g., 20V) with eachsubsequent pulse voltage increasing incrementally until the cell isprogrammed or a maximum programming voltage is reached. Unselected wordlines are biased at V_(pass) (e.g., 10V). Selected bit lines are biasedat 0V while unselected bit lines are biased V_(CC) to inhibit theprogram operation for those series strings.

A verification (read) operation with a selected word line voltage of 0Vis then performed to determine if the floating gate is at the propervoltage (e.g., 0.5V). In one embodiment, the unselected word linevoltages can be any voltage equal to or greater than ground potential.The bit lines are precharged to V_(CC) while the SG(D) and SG(S) areselected. Each of the memory cells is programmed/verified in asubstantially similar fashion.

FIG. 3 illustrates a schematic diagram of a data latch circuit 300 ofthe present invention coupled to a portion of a series string of memorycells 340 of a NAND flash memory array.

The latch circuit 300 is comprised of two inverters 304, 305 that arecoupled to a DATA node and a DATA* node that is the inverse of the DATAnode. Three control transistors 301, 302, and 306 are coupled to theinverters 304, 305 to control the operation of the latch circuit 300.Two of the transistors 301, 302 control which side (i.e., DATA or DATA*)of the latch 304, 305, in response to active high RDA and RDB controlsignals, is coupled to the SENSE_OUT node. The other transistor 306 is areset transistor that has an active high PRST signal coupled to the gateto control when the transistor is turned on to pull the DATA* output ofthe latch to ground.

The series string of memory cells 340, in one embodiment, is comprisedof thirty-two floating gate flash memory cells as illustrated in FIG. 2.Each of the memory cells in unselected rows that are biased by the“WLUNSEL” voltage that is coupled to each of the “unselected” wordlines. The selected word line is biased by the “WLSEL” voltage.Alternate embodiments can use other quantities of memory cells in eachseries string as well as different non-volatile memory cell technology.

The select gate source transistor 325 and the select gate draintransistor 324 are on opposing sides of the string 340. The seriesstring 340 is then coupled to the global bit line GBL that is coupled toan NMOS control transistor 322 that controls access to the senseamplifier by the string 340. The gate of the control transistor 322 isbiased by a “SENSE” voltage that controls operation of the transistor322.

A precharge PMOS transistor 320 couples the NMOS control transistor 322to V_(CC) for precharging the bit line during a read operation. Alogical low level on the gate of the PMOS transistor 320 turns thetransistor on.

A sense amplifier output transistor 310 has its gate coupled between theNMOS transistor 322 and the PMOS transistor 320. A logical high on thegate of this transistor 310 pulls the latch circuit 300 to ground aswill be described subsequently. A logical low on the gate causes thelatch circuit 300 to see a high impedance state.

Operation of the latch circuit 300 of FIG. 3 is discussed with referenceto the threshold voltage distributions illustrated in FIGS. 4 and 5.Each distribution, 401-404 of FIGS. 4 and 501-504 of FIG. 5, representsa different MLC state. The MLC data stored in each cell represents twopages of data, page 1 and page 0 (i.e., P1-P0).

FIG. 4 illustrates the threshold voltage distributions 401-404 forreading page 1 (P1) of the memory cells. The most negative state 401 isa logical “11” state. The next state 402 is the logical “10” state. Thefollowing state 403 is the logical “00” state. The most positive state404 is the logical “01” state. The read voltage, RD2, that is applied tothe selected word line as the “WLSEL” voltage is illustrated between themiddle two states 402, 403.

FIG. 5 illustrates the threshold voltage distributions 501-504 forreading page 0 (P0) of the memory cells. The most negative state 501 isa logical “11” state. The next most positive state 502 is the logical“10” state. The following state 503 is a logical “00” state. The mostpositive state 504 is the logical “01” state. The read voltages, RD1 andRD3, are applied to the selected word line as the “WLSEL” voltage. Theread 1 voltage (i.e., RD1) is between the first and second states 501,502. The read 3 voltage (i.e., RD3) is between the last two states 503,504.

Referring to FIGS. 3 and 4, the first state (i.e., logical 11) 401 isread by the following procedure. At a first time, t₀, the PRST signal isa logical 1 and RDA is a logical 0. This results in the latch circuitDATA* signal being a logical 0 and DATA is loaded with a logical 1.

At time t₁, the PRST signal is a logical 0 to turn off the transistor306. The memory cell transistor 330 is coupled to the selected word linebias WLSEL that is now at the read voltage RD2 as illustrated in FIG. 4.The sense amplifier then performs a sense operation as is well known inthe art. After the sense operation, RDA is a logical 1 to turn on itsrespective transistor 301 and RDB is kept at a logical 0 to keep thetransistor 302 turned off, thus connecting the DATA node of the latch tothe SENSE_OUT node that is now floating. This results in the logical 1(i.e., DATA) of page 1 of the first state 401 being read.

The second state (i.e., logical 10) 402 is read by the followingprocedure. At a first time, t₀, the PRST signal is a logical 1 and RDAis a logical 0. This results in the latch circuit DATA* signal being alogical 0 and DATA is loaded with a logical 1.

At time t₁, the PRST signal is a logical 0 to turn off the transistor306. The memory cell transistor 330 is coupled to the selected word linebias WLSEL that is now at the read voltage RD2 as illustrated in FIG. 4.The sense amplifier then performs a sense operation as is well known inthe art. After the sense operation, RDA is a logical 1 to turn on itsrespective transistor 301 and RDB is kept at a logical 0 to keep thetransistor 302 turned off, thus connecting the DATA node of the latch tothe SENSE_OUT node that is now floating. This results in the logical 1(i.e., DATA) of page 1 of the second state 402 being read.

The third state (i.e., logical 00) 403 is read by the followingprocedure. At a first time, t₀, the PRST signal is a logical 1 and RDAis a logical 0. This results in the latch circuit DATA* signal being alogical 0 and DATA is loaded with a logical 1.

At time t₁, the PRST signal is a logical 0 to turn off the transistor306. The memory cell transistor 330 is coupled to the selected word linebias WLSEL that is now at the read voltage RD2 as illustrated in FIG. 4.The sense amplifier then performs a sense operation as is well known inthe art. After the sense operation, RDA is a logical 1 to turn on itsrespective transistor 301 and RDB is kept at a logical 0 to keep thetransistor 302 turned off, thus connecting the DATA node of the latch tothe SENSE_OUT node that is now at a logical 0. This results in thelogical 0 (i.e., DATA) of page 1 of the third state 403 being read.

The fourth state (i.e., logical 01) 404 is read by the followingprocedure. At a first time, t₀, the PRST signal is a logical 1 and RDAis a logical 0. This results in the latch circuit DATA* signal being alogical 0 and DATA is loaded with a logical 1.

At time t₁, the PRST signal is a logical 0 to turn off the transistor306. The memory cell transistor 330 is coupled to the selected word linebias WLSEL that is now at the read voltage RD2 as illustrated in FIG. 4.The sense amplifier then performs a sense operation as is well known inthe art. After the sense operation, RDA is a logical 1 to turn on itsrespective transistor 301 and RDB is kept at a logical 0 to keep thetransistor 302 turned off, thus connecting the DATA node of the latch tothe SENSE_OUT node that is now at a logical 0. This results in thelogical 0 (i.e., DATA) of page 1 of the fourth state 404 being read.

Referring to FIGS. 3 and 5, the first state 501 of page 0 (i.e., P0) isread by the following procedure. At a first time, t₀, the PRST signal isa logical 1 and RDA is a logical 0. This results in the latch circuitDATA* signal being a logical 0 and DATA is loaded with a logical 1.

At time t₁, the PRST signal is a logical 0 to turn off the transistor306. The memory cell transistor 330 is coupled to the selected word linebias WLSEL that is now at the read voltage RD1 as illustrated in FIG. 5.The sense amplifier then performs a sense operation as is well known inthe art. After the sense operation, RDA is a logical 1 to turn on itsrespective transistor 301 and RDB is kept at a logical 0 to keep thetransistor 302 turned off thus connecting the DATA node of the latch tothe SENSE_OUT node that is now floating. This results in the node DATAbeing a logic 1.

At time t₂, the PRST signal is a logical 0 to turn off the transistor306. The memory cell transistor 330 is coupled to the selected word linebias WLSEL that is now at the read voltage RD3 as illustrated in FIG. 5.The sense amplifier then performs a sense operation as is well known inthe art. After the sense operation, RDA is a logical 0, RDB is a logical1 to turn on its respective transistor 302 thus connecting the DATA*node of the latch formed by the inverters 304, 305 to the SENSE_OUT nodethat is now floating. This results in the logical 1 (i.e., DATA) of page0 of the first state 501 being read.

The second state (i.e., logical 10) 502 is read by the followingprocedure. At a first time, t₀, the PRST signal is a logical 1 and RDAis a logical 0. This results in the latch circuit DATA* signal being alogical 0 and DATA is loaded with a logical 1.

At time t₁, the PRST signal is a logical 0 to turn off the transistor306. The memory cell transistor 330 is coupled to the selected word linebias WLSEL that is now at the read voltage RD1 as illustrated in FIG. 5.The sense amplifier then performs a sense operation as is well known inthe art. After the sense operation, RDA is a logical 1 to turn on itsrespective transistor 301 and RDB is kept at a logical 0 to keep thetransistor 302 turned off thus connecting the DATA node of the latch tothe SENSE_OUT node that is now a logical 0. This results in the nodeDATA being a logic 0.

At time t₂, the PRST signal is a logical 0 to turn off the transistor306. The memory cell transistor 330 is coupled to the selected word linebias WLSEL that is now at the read voltage RD3 as illustrated in FIG. 5.The sense amplifier then performs a sense operation as is well known inthe art. After the sense operation, RDA is a logical 0, RDB is a logical1 to turn on its respective transistor 302 thus connecting the DATA*node of the latch formed by the inverters 304, 305 to the SENSE_OUT nodethat is now floating. This results in the logical 0 (i.e., DATA) of page0 of the second state 502 being read.

The third state (i.e., logical 00) 503 is read by the followingprocedure. At a first time, t₀, the PRST signal is a logical 1 and RDAis a logical 0. This results in the latch circuit DATA* signal being alogical 0 and DATA is loaded with a logical 1.

At time t₁, the PRST signal is a logical 0 to turn off the transistor306. The memory cell transistor 330 is coupled to the selected word linebias WLSEL that is now at the read voltage RD1 as illustrated in FIG. 5.The sense amplifier then performs a sense operation as is well known inthe art. After the sense operation, RDA is a logical 1 to turn on itsrespective transistor 301 and RDB is kept at a logical 0 to keep thetransistor 302 turned off thus connecting the DATA node of the latch tothe SENSE_OUT node that is now at a logical 0. This results in the nodeDATA being a logic 0.

At time t₂, the PRST signal is a logical 0 to turn off the transistor306. The memory cell transistor 330 is coupled to the selected word linebias WLSEL that is now at the read voltage RD3 as illustrated in FIG. 5.The sense amplifier then performs a sense operation as is well known inthe art. After the sense operation, RDA is a logical 0, RDB is a logical1 to turn on its respective transistor 302 thus connecting the DATA*node of the latch formed by the inverters 304, 305 to the SENSE_OUT nodethat is now floating. This results in the logical 0 (i.e., DATA) of page0 of the third state 503 being read.

The fourth state (i.e., logical 01) 504 is read by the followingprocedure. At a first time, t₀, the PRST signal is a logical 1 and RDAis a logical 0. This results in the latch circuit DATA* signal being alogical 0 and DATA is loaded with a logical 1.

At time t₁, the PRST signal is a logical 0 to turn off the transistor306. The memory cell transistor 330 is coupled to the selected word linebias WLSEL that is now at the read voltage RD1 as illustrated in FIG. 5.The sense amplifier then performs a sense operation as is well known inthe art. After the sense operation, RDA is a logical 1 to turn on itsrespective transistor 301 and RDB is kept at a logical 0 to keep thetransistor 302 turned off thus connecting the DATA node of the latch tothe SENSE_OUT node that is now at a logical 0. This results in the nodeDATA being a logic 0.

At time t₂, the PRST signal is a logical 0 to turn off the transistor306. The memory cell transistor 330 is coupled to the selected word linebias WLSEL that is now at the read voltage RD3 as illustrated in FIG. 5.The sense amplifier then performs a sense operation as is well known inthe art. After the sense operation, RDA is a logical 0, RDB is a logical1 to turn on its respective transistor 302 thus connecting the DATA*node of the latch formed by the inverters 304, 305 to the SENSE_OUT nodethat is now at a logical 0. This results in the logical 1 (i.e., DATA)of page 0 of the fourth state 504 being read.

A read-modify-write technique is used to generate the inhibit voltage ofthe program operation of a NAND cell when its V_(t) pass the verifylevel. One embodiment for a circuit to accomplish this is illustrated inFIG. 6.

The circuit is comprised of a latch 600, made up of two inverters 602,603, with a control transistor 605. The gate of the transistor 605 isconnected to “CSENSE1” control signal that goes high when a cell hasbeen verified as programmed during a verify operation. The drain of thetransistor 605 is shown coupled to a circuit ground in dotted lines. Thedotted lines represent the functional equivalent of the circuit to whichthe transistor 605 is coupled as illustrated subsequently with referenceto FIG. 7.

The read-modify-write technique involves storing the data to beprogrammed in the latch 600 as DATA during the program pulse and thenmodify it when the V_(t) of the cell has become higher than apredetermined verify value. In other words, the cell has beensuccessfully programmed. For example, assuming that DATA to beprogrammed is a logical 0 and while the “CSENSE1” signal is low, thetransistor 605 is turned off and the latch output through the invertergate 606 is a logical “0”. The inverter gate 606 is enabled whenever theprogram pulse (i.e., pgm_pulse) goes high. During this time, the logicallow signal is applied to the bit line thus allowing the cells on theselected word line to be programmed.

When CSENSE1 goes high after the verify operation has passed, DATA* ispulled to a logical 0 through the transistor 605 and the output of theinverter gate 606 is a logical high. This V_(CC) bias is applied to thebit line, thereby inhibiting the program operation.

FIG. 7 illustrates the data latches and support circuitry of the presentinvention. This circuit includes the first data latch circuit 300 asillustrated in FIG. 3 and the second data latch circuit 600 asillustrated in FIG. 6. The pass transistors 701, 702 and supportcircuitry 704, 705 that ties the latches 300, 600 together is alsoshown. A pull-up transistor 721 is coupled to a VFY_MATCH signal that isa logic high when the programmed data has been verified. A pull-downtransistor 720 is coupled to the first latch circuit 300 with a“PULLDOWN_EN” signal coupled to the gate that goes high to turn on thetransistor 720.

After the read-modify-write operation described previously, VFY_MATCH isprecharged or pulled up to a logical 1 level. Then if all the bits to beprogrammed are modified from 0 to 1, the node DATA* will be at a logical0 and the common line VFY_MATCH will stay at a logical 1. If some of thebits to be programmed are still at a logical 0 after theread-modify-write operation, the information regarding the bits failingto verify can be extracted.

To extract the bit information, PASS1 is set high, PASS0 is set low, andPULLDOWN_EN is set to a high state. The VFY_MATCH line is pulled down ifany of page 0 (P0) die not pass the verify operation during a P0programming.

By making PASS1=0, PASS0=1, and PULLDOWN_EN=1, the VFY_MATCH line willbe pulled down if any of P1, having P0=0, did not pass the verifyoperation. By making PASS1=1, PASS0=1, and PULLDOWN_EN=1, the VFY_MATCHline is pulled down if any of the data to be programmed did not pass theverify operation.

To verify the programming of P0, the first latch circuit 300 is presetso that DATA node is a logical 1. P0=0 is loaded into the second latchcircuit 600 at node DATA. A verify voltage, VFY1 is applied to WLSEL andPASS1=1. In one embodiment, the VFY1 voltage is located between thefirst two MLC states. A sense operation is then performed by the senseamplifier as is well known in the art. After the sense operation,CSENSE1=1.

If the threshold voltage sensed is greater than or equal to VFY1,SENSE_OUT=0, NODEB=0, and P0 becomes a logical 1. The programming isinhibited as explained previously for the next programming pulse.

If the threshold voltage sensed is less than VFY1, SENSE_OUT is in ahigh impedance state and P0 stays a logical low. The programmingoperation is then performed again.

To verify the programming of P1 with VFY3 voltage when P0=1, P0 is readand stored in the first latch 300 at the DATA node during the beginningof the programming operation. P1=0 is loaded into the second latch 600at the DATA node. A verify voltage, VFY3 is used to bias the selectedword line as WLSEL. VFY3, in one embodiment, is a voltage locatedbetween the third and fourth MLC states. VFY2, in one embodiment, is avoltage located between the second and third MLC states.

The gates of the pass transistors 701, 702 are biased as PASS1=1 andPASS0=0. A sense operation is then performed. After the sense amplifierhas accomplished the sense operation, CSENSE1=1. If the thresholdvoltage, V_(t), is greater than or equal to VFY3, the SENSE_OUT node=0and NODEB=0. P0 becomes a logical 1 and the programming operation isinhibited for the next programming pulse only for cells having P0=1. IfV_(t) is less than VFY3, the SENSE_OUT node is high impedance and P0stays as a logical 0. The programming operation is performed again.

To verify the programming of P1 with VFY2 when P0=0, P0 is read andloaded into the first latch circuit at the DATA node during thebeginning of the programming operation. The DATA node of the secondlatch 600 is loaded with P1=0. A verify voltage, VFY2, biases theselected word line as the WLSEL voltage. PASS0=1 and PASS1=0. A senseoperation is then performed by the sense amplifier. After the senseoperation, CSENSE1=1.

If the sensed threshold voltage, V_(t), is greater than or equal toVFY3, the SENSE_OUT node is a logical 0, NODEB=0, and P0 becomes alogical 1. The next programming operation is inhibited only for cellshaving P1=0.

If the sensed threshold is less than VFY3, the SENSE_OUT node is in ahigh impedance state. In this case, P0 stays as a logical 0 and theprogramming operation is performed again.

FIG. 8 illustrates a functional block diagram of a memory device 800that can incorporate the flash memory array and programming methodembodiments of the present invention. The memory device 800 is coupledto a processor 810 that is responsible for executing the software driverof the present invention for writing SLC data into an MLC device. Theprocessor 810 may be a microprocessor or some other type of controllingcircuitry. The memory device 800 and the processor 810 form part of amemory system 820. The memory device 800 has been simplified to focus onfeatures of the memory that are helpful in understanding the presentinvention.

The memory device includes an array of flash memory cells 830 asdescribed above with reference to FIG. 8. The memory array 830 isarranged in banks of rows and columns. The control gates of each row ofmemory cells is coupled with a word line while the drain and sourceconnections of the memory cells are coupled to bitlines. As is wellknown in the art, the connections of the cells to the bitlinesdetermines whether the array is a NAND architecture, an ANDarchitecture, or a NOR architecture.

An address buffer circuit 840 is provided to latch address signalsprovided on address input connections A0-Ax 842. Address signals arereceived and decoded by a row decoder 844 and a column decoder 846 toaccess the memory array 830. It will be appreciated by those skilled inthe art, with the benefit of the present description, that the number ofaddress input connections depends on the density and architecture of thememory array 830. That is, the number of addresses increases with bothincreased memory cell counts and increased bank and block counts.

The memory device 800 reads data in the memory array 830 by sensingvoltage or current changes in the memory array columns usingsense/buffer circuitry 850. The sense/buffer circuitry, in oneembodiment, is coupled to read and latch a row of data from the memoryarray 830. Data input and output buffer circuitry 860 is included forbi-directional data communication over a plurality of data connections862 with the controller 810. Write circuitry 855 is provided to writedata to the memory array.

Control circuitry 870 decodes signals provided on control connections872 from the processor 810. These signals are used to control theoperations on the memory array 830, including data read, data write(program), and erase operations. The control circuitry 870 may be astate machine, a sequencer, or some other type of controller.

The flash memory device illustrated in FIG. 8 has been simplified tofacilitate a basic understanding of the features of the memory. A moredetailed understanding of internal circuitry and functions of flashmemories are known to those skilled in the art.

FIG. 9 is an illustration of an exemplary memory module 900. Memorymodule 900 is illustrated as a memory card, although the conceptsdiscussed with reference to memory module 900 are applicable to othertypes of removable or portable memory, e.g., USB flash drives, and areintended to be within the scope of “memory module” as used herein. Inaddition, although one example form factor is depicted in FIG. 9, theseconcepts are applicable to other form factors as well.

In some embodiments, memory module 900 will include a housing 905 (asdepicted) to enclose one or more memory devices 910, though such ahousing is not essential to all devices or device applications. At leastone memory device 910 is a non-volatile memory [including or adapted toperform elements of the invention]. Where present, the housing 905includes one or more contacts 915 for communication with a host device.Examples of host devices include digital cameras, digital recording andplayback devices, PDAs, personal computers, memory card readers,interface hubs and the like. For some embodiments, the contacts 915 arein the form of a standardized interface. For example, with a USB flashdrive, the contacts 915 might be in the form of a USB Type-A maleconnector. For some embodiments, the contacts 915 are in the form of asemi-proprietary interface, such as might be found on COMPACTFLASHmemory cards licensed by SANDISK Corporation, MEMORYSTICK memory cardslicensed by SONY Corporation, SD SECURE DIGITAL memory cards licensed byTOSHIBA Corporation and the like. In general, however, contacts 915provide an interface for passing control, address and/or data signalsbetween the memory module 900 and a host having compatible receptors forthe contacts 915.

The memory module 900 may optionally include additional circuitry 920which may be one or more integrated circuits and/or discrete components.For some embodiments, the additional circuitry 920 may include a memorycontroller for controlling access across multiple memory devices 910and/or for providing a translation layer between an external host and amemory device 910. For example, there may not be a one-to-onecorrespondence between the number of contacts 915 and a number of I/Oconnections to the one or more memory devices 910. Thus, a memorycontroller could selectively couple an I/O connection (not shown in FIG.9) of a memory device 910 to receive the appropriate signal at theappropriate I/O connection at the appropriate time or to provide theappropriate signal at the appropriate contact 915 at the appropriatetime. Similarly, the communication protocol between a host and thememory module 900 may be different than what is required for access of amemory device 910. A memory controller could then translate the commandsequences received from a host into the appropriate command sequences toachieve the desired access to the memory device 910. Such translationmay further include changes in signal voltage levels in addition tocommand sequences.

The additional circuitry 920 may further include functionality unrelatedto control of a memory device 910 such as logic functions as might beperformed by an ASIC (application specific integrated circuit). Also,the additional circuitry 920 may include circuitry to restrict read orwrite access to the memory module 900, such as password protection,biometrics or the like. The additional circuitry 920 may includecircuitry to indicate a status of the memory module 900. For example,the additional circuitry 920 may include functionality to determinewhether power is being supplied to the memory module 900 and whether thememory module 900 is currently being accessed, and to display anindication of its status, such as a solid light while powered and aflashing light while being accessed. The additional circuitry 920 mayfurther include passive devices, such as decoupling capacitors to helpregulate power requirements within the memory module 900.

CONCLUSION

In summary, the embodiments of the present invention handle two bitsfrom an MLC memory device with only a single latch. Only one additionallatch is used to implement MLC programming with a read-modify-write andverify during a programming operation.

Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat any arrangement that is calculated to achieve the same purpose maybe substituted for the specific embodiments shown. Many adaptations ofthe invention will be apparent to those of ordinary skill in the art.Accordingly, this application is intended to cover any adaptations orvariations of the invention. It is manifestly intended that thisinvention be limited only by the following claims and equivalentsthereof.

1. A memory device comprising: a memory array comprising a plurality ofmemory cells; and a memory latch circuit coupled to the memory array,the circuit comprising: a first latch having a node and an invertednode; a first control means coupled between an output and the node suchthat the node is coupled to the output in response to a state of thefirst control means; a second control means coupled between the outputand the inverted node such that the inverted node is coupled to theoutput in response to a state of the second control means; a resetcircuit coupled to the inverted node for resetting the first latch to aknown state; and a second latch having a node and an inverted node. 2.The device of claim 1 and further including: a sense controller coupledto the inverted node of the second latch; and an output gate coupled tothe inverted node of the second latch such that an output of the outputgate is an output of the second latch.
 3. The device of claim 1 whereinthe sense controller selectively pulls the inverted node to groundpotential in response to a control sense signal.
 4. The device of claim3 wherein the control sense signal is coupled to a gate of the sensecontroller and turns on the sense controller, when at a logical highstate, to pull the inverted node to ground potential.
 5. The device ofclaim 1 wherein the first and second latches are each comprised of apair of inverter gates coupled such that the output of each gate isconnected to an input of the other gate.
 6. A flash memory devicecomprising: a memory array comprising a plurality of non-volatile memorycells arranged in a plurality of a series strings having a bit line; anda memory latch circuit comprising: a first latch having a node and aninverted node; a first output control circuit coupled between a firstlatch output and the node; a second output control circuit coupledbetween the output and the inverted node; a reset control circuitcoupled to the inverted node; a second latch having a node and aninverted node; a sense control circuit coupled to the inverted node; andan output gate coupled to the inverted node such that an output of theoutput gate is coupled to the bit line.
 7. The device of claim 6 whereinthe memory array is arranged in a NAND architecture.
 8. The device ofclaim 6 and further including a sense control circuit configured tocouple the bit line to the output of the first latch when set to apredetermined state.
 9. The device of claim 6 wherein each of theplurality of memory cells is adapted to store at least two bits of data.10. The device of claim 6 wherein each memory cell is a floating gatememory cell.
 11. The device of claim 6 and further including word linesthat couple rows of memory cells.
 12. A method for reading a first pageof data of multiple pages of a multiple level cell memory device, themethod comprising: resetting a first bit line latch, of a plurality ofbit line latches, at a first time, each bit line being coupled to adifferent bit line latch, each bit line latch having an inverted node, anon-inverted node, and a latch output; biasing a selected word line ofthe memory device with ground potential at the first time; biasing theselected word line with a read voltage greater than ground potential ata second time; and coupling the non-inverted node to the latch output atthe second time to read the page one data.
 13. The method of claim 12and further including biasing unselected word lines at a V_(pass)voltage that is greater than ground potential.
 14. The method of claim12 and further comprising selecting other word lines of a memory blockat different times to read a first page of data from each word line. 15.The method of claim 12 wherein resetting the first bit line latchcomprises coupling the inverted node to circuit ground through a resettransistor.
 16. The method of claim 12 and further including reading asecond page of data of the multiple pages comprising: resetting thelatch at a third time after the second time; biasing the selected wordline of the memory device at ground potential at the third time;coupling the non-inverted node to the first bit line latch output at afourth time; biasing the selected word line at a first read voltage,greater than or equal to ground potential, at the fourth time; couplingthe inverted node to the latch output at a fifth time; and biasing theselected word line at a second read voltage, greater than the first readvoltage, at the fifth time to read the page zero data.
 17. The method ofclaim 16 wherein the reset transistor is turned on only during the thirdtime.
 18. The method of claim 16 wherein the non-inverted node iscoupled to the output by turning on a first control transistor and theinverted node is coupled to the output by turning on a second controltransistor.
 19. The method of claim 16 wherein the first read voltage isbetween first and second threshold voltage distributions and the secondread voltage is between third and fourth threshold voltagedistributions.
 20. A memory system comprising: a memory devicecomprising a multiple level memory cell array having bit lines coupledto series strings of memory cells, each memory cell array arranged inmemory blocks and further comprising: a different memory latch circuitcoupled to each bit line of the memory block and comprising: a firstlatch having a non-inverted node and an inverted node; a first circuitcoupled between an output and the non-inverted node such that thenon-inverted node is coupled to the output when the first circuit is ina conducting state; a second circuit coupled between the output and theinverted node such that the inverted node is coupled to the output whenthe second circuit is in the conducting state and the first circuit isin a non-conducting state; and a reset circuit coupled to the invertednode for resetting the memory latch circuit to a predetermined state; asecond latch having a non-inverted node and an inverted node; a sensecontrol circuit coupled to the inverted node of the second latch; and anoutput circuit coupled to the inverted node of the second latch suchthat an output of the output circuit is coupled to the bit line.